====== Circuit design details====== // [[ctsd_adc_90nm|go to project home]] // ===== ADC noise budgetting ===== * For a dynamic range of 86dB, measured at -15dBFS input signal (at 85C) ^ Noise source ^ noise spec ^ Noise referred to ADC i/p ^ %contribution| ^ Integrator1 Amp| 10 uV|20 uV|20%| ^ ADC i/p resistors| 23.3 uV|23.3 uV|30%| ^ DAC isource| 23.3 uV (referred to i/p resistors)|23.3 uV|30%| ^ Quantization| 96 dB |19 uV|20%| * ADC i/p resistor is chosen to be 400 ohms single ended. ===== Integrator1 OTA ===== * Two different architectures are used to evaluate modulator performance with different mismatch-levels in the replica-o/p-current sources. The summary of the results are given here --> {{:updates_amp1_architecture.pdf?800}} * **OTA1 architecture:** 2-stage amplifier with cap-coupled feedforward compensation {{:amp1.png?1000}} * ** Small-signal/Noise performance ** ^ Parameter:^worst value^worst corner (mos,temp,cap,res)| ^ DC gain:|49.8 dB |SF_mos, 85C, min_cap | ^ UGB:|2.61 GHz |FS_mos, 85C, max_cap | ^ Phase Margin:|48.3 degree |SS_mos, 85C, min_cap | ^ Amp i/p noise:|10.3 uV |SS_mos, 85C, min_cap | * **Random Mismatch :** * The o/p NMOS drain current is the most sensitive to random mismatch. The random current variation in the o/p NMOS transistor is under 10%. * The random current variation in the o/p PMOS transistor is under 3%. * **Total supply current (OTA + bias)= 5.54mA** * ** SNDR performance : ** * SNDR vs Replica matching (FF_mos, 85C, min_cap) ^ replica matching :^90%^95%^98%^100%^103%^105%^108%^110%| ^ SNDR for 100mV i/p signal:|96.8 dB|97.7 dB|97.1 dB|96.2 dB|96.2 dB|97.5 dB| 97.6 dB|96.6 dB| ^ SNDR for 300mV i/p signal:|94.6 dB |94.7 dB |96.2 dB|94.7 dB|94.7 dB|94.5 dB|95.4 dB|95.4 dB| * SNDR across corners (10% replica matching) ^ Parameter:^worst value^worst corner (mos,temp,cap,res)| ^ SNDR for 100mV i/p signal:|95.7 dB |SF_mos, 85C, min_cap | ^ SNDR for 300mV i/p signal:|94.1 dB |FS_mos, 0C, min_cap |