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| Name: |
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Dr.
Nitin Chandrachoodan
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| Designation: |
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Assistant Professor
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| Office Address: |
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Department of Electrical
Engineering
IIT Madras
Chennai - 600 036
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| Phone number: |
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+91 - 44 - 2257
4432 (O)
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| Ph.D. From: |
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University of Maryland,
College Park, USA
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| e-mail address(es): |
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nitin[AT]ee.iitm.ac.in
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| Personal
home page: |
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http://www.ee.iitm.ac.in/~nitin/
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Areas
of Research: |
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DSP
Architectures
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CAD
for ICs
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VLSI
Design
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Most
recently taught courses at IIT Madras and elsewhere: |
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- EC209 Microprocessors
and Computer Organization
- EE 462 Advanced Microelectronics
Lab. II
- EE 510Mapping DSP
Algorithms to Architectures
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Most
recently published papers: |
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N.
Chandrachoodan, S. S. Bhattacharyya, and
K. J. R. Liu. The hierarchical
timing pair model for multirate DSP applications.
IEEE Transactions on Signal Processing,
52(5):1209-1217, May 2004.
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N. Chandrachoodan. Performance
Analysis and Hierarchical Timing for DSP
System Synthesis. PhD thesis, Department
of Electrical and Computer Engineering,
University of Maryland, College Park, August
2002.
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N. Chandrachoodan, S. S. Bhattacharyya,
and K. J. Ray Liu. High-level synthesis
of DSP applications using adaptive negative
cycle detection. EURASIP Journal on Applied
Signal Processing, 2002(9):893-907, September
2002.
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N. Chandrachoodan, S. S. Bhattacharyya,
and K. J. R. Liu. Adaptive negative
cycle detection in dynamic graphs. In Proceedings
of the International Symposium on Circuits
and Systems, pages V-163-V-166, Sydney,
Australia, May 2001.
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N. Chandrachoodan, S. S. Bhattacharyya,
and K. J. R. Liu. An efficient
timing model for hardware implementation
of multirate dataflow graphs. In Proceedings
of the International Conference on Acoustics,
Speech, and Signal Processing, Salt Lake
City, Utah, May 2001. 4 pages.
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