| PhD Seminar

Name of the Speaker: Mr. Aditya Narayanan (EE15D412)
Guide: Prof. Nagendra Krishnapura
Venue: ESB-210B (Conference Hall)
Date/Time: 18th December 2023 (Monday), 12:00 PM
Title: A 6–12 GHz Fractional-N Frequency Synthesizer with a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

Abstract

The talk will present a frequency synthesizer for generating quadrature LO waveforms covering an octave range of 6–12 GHz. Modulus-dependent delay (MDD) of the feedback divider increases jitter in fractional-N phase-locked loops (PLL). A new digital technique, which can be realized with minor modifications to the conventional digital delta-sigma modulator (DDSM), is implemented to overcome this effect. The synthesizer uses two voltage-controlled oscillators (VCO) operating from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). The prototype synthesizer in 65 nm CMOS occupies 0.54 sq. mm and consumes 66 mW at the highest frequency from a 1 V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400 fs, 300 fs, 500 fs in the 6–8, 8–10, and 10–12 GHz ranges, respectively. The worst-case reference spurs are below −60 dBc and the fractional spurs are below −31 dBc.