| MS Seminar

Name of the Speaker: CARLTON D’SILVA (EE20S058)
Guide: Dr. RadhaKrishna Ganti
Co-Guide: Prof. Nitin Chandrachoodan
Venue: ESB-244 (Seminar Hall)
Date/Time: 9th November 2023 (Thursday), 2:00 PM
Title: Timing and Multi-Antenna Phase Synchronization in a 5G-NR RRH

Abstract

In 5G-NR, physical layer is used to process bits received from the higher layers and transmit them over the air (OTA). The Remote Radio Head (RRH) includes signal processing followed by the antenna subsystem. The advent of functional splits over the physical layer paved way in decreasing the complexity of RRH by pushing major signal processing blocks towards the Base Band Unit (BBU), but the requirement to form narrow beams in 5G led to the introduction of multiple antennas and increases the need to synchronize these multiple antennas. There is always a necessity in designing a least complicated RRH that serves the system requirements laid by 3GPP.

The FPGA based implementation as stated in this talk covers various design aspects, implementation strategies and algorithms that would contribute for a more efficient and less complicated digital section of the RRH. Development of the RRH has multiple steps like bringing up the FPGA board, defining the digital logic that sits on the programmable logic (PL) and the user applications that runs on the processor system (PS) of the FPGA. The digital section of the RRH is implemented on two different FPGAs called the Data Aggregator (DA) and the Digital Front-End (DFE). The Data Aggregator(DA) addresses the signal processing part of the RRH such as the Fronthaul Framer/De-framer and Layer to Antenna Mapper. DA acts as the master and controls upto four DFEs while the DFE withholds the latter part of the signal processing modules such as the GB Addition/GB Removal, IFFT/FFT, and DAC/ADC. My work primarily focuses on developing RTL modules such as Weighted OverLap and Add (WOLA), flood gate to preserve Time Division Duplexing (TDD) property of the system, antenna phase calibration subsystem which fetches the weights from the PS to the PL and uses these weights to do complex multiplication on the PL using DSP slices available on the FPGA facilitating directional signal transmission that enhances network efficiency and user experience.