| PhD Seminar

Name of the Speaker: Jaya Deepthi Bandarupalli (EE16D013)
Guide: Dr. Saurabh Saxena
Venue: ESB-210B (Conference Hall)
Online meeting link: https://meet.google.com/ydq-zwjz-tuu
Date/Time: 25th August 2023 (Friday), 10 AM
Title: Design Techniques for a 0.63-7.5Gb/s Rapid On/Off Clock and Data Recovery with <50ns Turn-on Time

Abstract

Clock and data recovery (CDR) is essential to serial links catering to high-speed data transfer for a wide range of wireline applications. Knowing the nominal data rate in embedded serial links helps recover the clock frequency with an independent reference clock source on the CDR side. However, clock recovery faces severe challenges in servers and data centers where CDR frequently transitions between data rates and on-and-off states even when the nominal data rate is known. For an energy-efficient data transfer, the power consumption should be proportional to data requirements, and serial links should not operate with the peak data rates if not required. A 2X variation in the peak data rate and rapid on/off (ROO) clock recovery loop facilitates significant energy savings.

In this regard, we present a rapid on/off 0.63-7.5Gb/s digital clock and data recovery with a low turn-on time and recovered clock jitter. The CDR employs a fast-on 1.875-3.75GHz digitally controlled oscillator followed by a 2X integer-N PLL. The DCO incorporates an eight-bit digitally controlled phase interpolator embedded in a 6-12X injection-locked clock multiplier for fast turn-on and low O/P jitter. DCO's O/P is filtered using the fast-on PLL while generating the sampling clock phases for the half-rate CDR. Fabricated in the TSMC 65\,nm process, the CDR recovers the clock with <1.3ps rms jitter while dissipating 26.6mW at 7.5Gb/s and 14.4mW at 3.75Gb/s. Duty-cycling the CDR operation lowers the average data rates to 0.63Gb/s with less than 55ns turn-on time and 1.6s on/off period.

Second, we present a two-stage cascaded clock multiplier with roughly constant energy consumption across 2.5-5.0GHz frequency range. The proposed clock multiplier consists of a reconfigurable delay-locked loop and edge combiner in the first stage while generating a 156.25-312.5MHz clock from 39.25 MHz reference clock frequency. An injection-locked clock multiplier with a frequency tracking loop in the second stage implements a 2.5-5.0GHz output clock. The clock generation architecture is optimized for the clock multiplication ratio in the two stages and overall power consumption. Designed in TSMC 65 nm CMOS process and characterized with post-layout simulations, the first-stage clock multiplier achieves an integrated jitter 1.396-0.607 psrms across 156.25-312.5 MHz frequency range at 1.15-2.82mW power consumption. The two-stage clock multiplier gives the total output jitter 1.5-0.9 psrms across 2.5-5.0GHz output frequency with 0.98-1.06mW/GHz power dissipation.