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Statistical timing yield optimization using discrete gate sizing

July 13, 2015 @ 3:00 pm - 4:00 pm

Speaker: S. Ramprasath (EE10D046)
     The entry into the nanometer regime of the process technologies has lead to an increase in the process parameter variations. Traditionally deterministic delays obtained by performing static timing analysis(STA) on the worst case corner was used to optimize circuits to meet the timing specification. This leads to pessimistic estimates of circuit delays and hence creates a power/area overhead. With the constraints on power/area becoming tighter especially for portable devices, it is vital that these overheads are eliminated. Statistical static timing analysis(SSTA) treats the gate delays as random variables to obtain a distribution for the circuit delay, which reduces the pessimism inherent in the worst case corner analysis.
Timing yield is the fraction of chips that meet the timing specification. Statistical gate sizing algorithms improve the timing yield by sizing up gates. Gates are chosen for resizing based on a metric called yield-gradient, which is the expected change in timing yield for a unit change in cost under consideration(area or power). These algorithms are typically iterative in nature, thereby requiring efficient techniques to evaluate the yield-gradient.
We define an effective yield gradient that takes into account fan-in and fan-out effects and derive an analytical expression for it. However, the correlations between the gate delays makes it a potentially expensive computation. We derive bounds for the mean and standard deviation of the circuit delay distribution. Using these bounds we obtain a simpler expression for the effective yield-gradient, which has similar accuracy to the numerical yield-gradient. Results on benchmarks indicate that the effective yield-gradient achieves the same target yield as the numerical approach with a similar area overhead at a fraction of run-time. We also propose a heuristic to resize multiple nodes in a single iteration, that helps in reducing the number of iterations required to converge at a required timing yield. Multi-node resize achieves an order of magnitude average speed-up compared to the numerical approach but has an average area penalty of 3%. The results are demonstrated using ITC’99 benchmarks synthesized in UMC 90nm technology.


July 13, 2015
3:00 pm - 4:00 pm
Event Category:


ESB 244


Prof. Vinita Vasudevan
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