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Power Electronics in VLSI : Design Challenges and Solutions

August 13, 2015 @ 3:00 pm - 5:00 pm

Speaker : Ignatius Bezzam

Abstract : Power  consumption is  a  burning  issue  in  high  performance  systems  based  on  deep submicron  (DSM)  processors  (CPUs  and  GPUs). Resonant circuit operation for power consumption improvements in high speed clocking applications has been extensively studied. The  energy  used  to  charge  the  clock  grid  node  each  period  can  be  recycled  within  the  LC resonant  tank  network  formed  by  the  large  global  clock  capacitance  and  integrated  inductors. Novel integration of resonant circuits that can save several watts of power across the Dynamic Voltage and Frequency range, in current DSM Processors and ASICs are discussed.

Bio :  Ignatius Bezzam received the B. Tech. degree from IIT Madras in 1983 and the M.S. Degree in electrical engineering from San Jose State University, California, in 1995. He received his Ph.D. degree in electrical engineering a from Santa Clara University, California in 2015.

After  his B.Tech, he worked in India for five years in Semi Conductor complex Ltd., TIFR  and CDAC . IN 1989 joined ICPT in Europe to work with the Italian group of CERN.

In the past, he has worked with at National Semiconductor (TI), Maxim Integrated Products, Toshiba, Raytheon (Fairchild) and Altierre.   He holds several patents in  Analog Mixed Signal design  and PLL IC design. He has publications in ISSCC, ISCAS, LASCAS and ESSCIRC conferences.  He has designed and released more than 30 silicon chips to production in Analog/Mixed-signal applications. His current interests include Analog/RF, High Speed Digital and Power Management.

He has taught as an adjunct lecturer in Santa Clara University  and conducted advanced  short courses at ICTP.


August 13, 2015
3:00 pm - 5:00 pm
Event Category:


ESB 244


Prof. Shanthi Pavan
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