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Optimizing Power-Accuracy Trade-off in Approximate Adders

December 10, 2018 @ 11:00 am - 12:00 pm

Date –10.12.2018

Time – 11:00 AM

Venue – ESB 234

Speaker – Celia D. (EE13D003)

Guide – Dr. Nitin Chandrachoodan

Co-Guide – Dr. Vinita Vasudevan



Most image and video processing applications are highly error tolerant since human eyes do not perceive small changes in the accuracy of the image or video output. At the same time, these applications are often run in handheld devices that demand very low power consumption.  In such applications, approximate computing is used so that we obtain reduction in power, delay and area, at the cost of reduced accuracy. Since adders form the basic building blocks in such applications,

several approximate adders have been proposed in the literature, each providing a trade-off between accuracy and resources. However, the power versus accuracy trade-off obtained in existing approximate adders is not optimal. In this work, we propose the median adder in which the approximate part of the sum is set to a constant that minimizes the error distance. Since the sum is set to a constant, dynamic power consumed is zero. Amongst the approximate adders, it gives the best trade-off between power and accuracy.


When approximate adders are used in a system, we need to solve an optimization problem to find the number of accurate and approximate bits for each adder for a given accuracy constraint. In order to do this, error models for approximate adders are required. We have proposed a general framework for modelling the error of two-part segmented approximate adders and derived analytical expressions for error statistics of various adders for inputs with arbitrary distribution.

In an image addition application, we use our expression derived for mean square error and show that it predicts the PSNR correctly.


All are cordially invited.



December 10, 2018
11:00 am - 12:00 pm
Event Category:
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