DATE : 21.04.2017
TIME : 11 AM
VENUE : ESB 244
SPEAKER : Vishal Tiwari (EE12D203)
GUIDE : Deleep R. Nair
Prof. Devendra Jalihal (Chairperson)
Prof. Amitava Das Gupta (M)
Prof. Shreepad Karmalkar (M)
Prof. S. Ramanathan (M) (CH)
Parameter variations in the transistor characteristics with the introduction of new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon-germanium (SiGe) at 32nm and beyond are useful over silicon in high-k metal gate technology based p-type MOSFETs because of higher mobility and lower threshold voltage (VT). However, the presence of germanium (Ge) inside the channel faces several challenges including higher gate-induced drain leakage (GIDL) and significant additional variability in the electrical parameters due to variation in Ge concentration and SiGe thickness. This poses a difficulty in achieving high yield integrated circuits with low power consumption. So, mitigating this effect is crucial for the variability aware device design of next generation CMOS technologies.
In this work, we have reported the effect of process implants on the systematic and random variations of leakage and performance characteristics of SiGe channel pFETs. Experimental results, a noise-like approach called the statistical impedance field method and atomistic Monte-Carlo simulations are used to report that the elimination of a process step i.e., pre-halo germanium (Ge) pre-amorphization impant (PAI) from the SiGe pFET process flow reduce OFF-state leakage and GIDL variations due to systematic variations but increases the time-zero (static) random GIDL and performance variations. This is attributed to random dopant position fluctuations in the extension and halo region for different bias voltages. However, we have shown that the increase in random variability without Ge PAI reduces for lower supply voltages. Thus, it offers advantages of reduced GIDL with same electrostatics, lower systematic variations and similar random variability for scaled voltages. These results will be helpful for variability aware device design of high VT planar SiGe pFET devices at low supply voltages.
All are cordially invited.