Time: 2:00 P.M.
Venue: ESB 234
Speaker: Vipul Bajaj (EE12S043)
Guide: Dr. Nagendra Krishnapura
High resolution successive approximation (SAR) analog to digital converters have been the architectural choice of preference for data acquisition and seismic monitoring applications. The area and the power requirements of the converter scale by a factor for 4 for every bit increase in the resolution. Even with this scaling, the raw matching of the components (capacitor-DAC) limit the accuracy of SAR converters to 12-bit. The techniques like calibration and trimming used to mitigate these process limitations are usually expensive in terms of area, cost and test time.
This work is focused to embed a SAR ADC in a delta-sigma loop, thereby allowing the use of dynamic element matching techniques to overcome this limitation. The delta-sigma loop also allows us to shape the quantization noise, and hence improve the resolution of the converter by trading off speed for accuracy. In this work 16-bit performance was achieved in a 0.6 um CMOS process by successfully implementing a first order delta-sigma loop around a 12-bit SAR with C-DAC matching limited to 12bits.