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Noise Analysis and Design of Ring Amplifier for usage in a Delta-Sigma ADC

February 6, 2018 @ 2:00 pm - 3:00 pm

TITLE : Noise Analysis and Design of Ring Amplifier for usage in a Delta-Sigma ADC

DATE : 06.02.2018 (Tuesday)

TIME :2:00pm – 3:00pm

VENUE : CSD 308

SPEAKER: Arnab Das (EE15S016)

GUIDE : Dr. Shanti Pavan

GTC Members :

Dr. Vinita Vasudevan (Chairperson)

Dr. Madhu Mutyam (M) (CS)

Dr. Qadeer Ahmad Khan  (M)

ABSTRACT

Technology scaling has made it difficult to realize high GBW op-amps required for precision applications in a power-efficient manner. As an alternative, simple CMOS inverter based solution such as Ring Amplifier is gaining popularity day-by-day, due to the properties like slew-based charging, rapid stabilization, compression immunity and performance scalability.  However, due to the mostly large-signal settling behavior, a proper understanding of the operation and estimation of different parameters of ring amplifier is not straightforward. Especially, the analysis of noise in such circuit is hardly discussed in open literature.

In this work, noise analysis of Ring Amplifier based on an existing adjoint network based technique for Linear Periodically Time Varying (LPTV) systems will be discussed. Additionally, a modified architecture of ring amplifier is proposed to enhance its robustness, area and power efficiency. The design of a ring amplifier, for its usage as the first stage integrator of a discrete-time ΔΣ modulator, shall be discussed. The modulator, designed in 65nm TI process, achieves a SNDR/DR of 99dB/102dB for a signal bandwidth of 62.5 KHz while consuming 0.9mW from 1.4V supply. The calculated Schreier FoM of the modulator is 177dB.

All are cordially invited.

Details

Date:
February 6, 2018
Time:
2:00 pm - 3:00 pm
Event Category:

Venue

CSD308
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