Speaker: Parthasarathy Nayak (EE13S054)
1200 Volt Silicon Carbide (SiC) MOSFET provides better conduction and switching performances compared to state of the art Si IGBTs. SiC MOSFET based power converters can operate at switching frequency more than 20 kHz due to almost five time reduction in switching time compared to Si IGBT.However, key obstacle to the superior performance of SiC MOSFET is the high frequency oscillation and overshoot in device voltage, current and gate voltage during switching transients. These oscillations result due to L-C network formed between parasitic inductances present in converter layout and device capacitances. Generally, IGBT based two level converter layout contains parasitic inductance in the range of 100 nH to 300 nH. IGBTs do not show considerable amount of voltage and current overshoot for this range of parasitic inductance due to comparatively slower switching speed. Popularity of SiC MOSFET in the industries can be increased manifold if it can be retrofitted in the existing IGBT based converter layouts. In this scenario, coexisting with moderate amount of parasitic inductance in converter layout yet exploiting the benefits of SiC MOSFET without sacrificing its switching speed (typically 50 to 60 nsec) is a challenge.
This problem can be addressed by appropriately controlling the gate signal of SiC MOSFET. In a conventional gate driver (CGD), gate resistance is kept fixed. Therefore there is no control on rise and fall of device voltage and current during all switching transients. This thesis proposes a complex programmable logic device (CPLD) based activegate driving (AGD) technique for SiC MOSFET. The proposed gate driversenses device voltage and current during every switching interval. During these intervals (typically 50-60 nsec) gate resistance are dynamically controlled. This dynamic variation of gate resistance actively controls device voltage and current overshoot without sacrificing its switching speed. As a result, SiC MOSFETs can effectively exhibit superior switching performance compared to Si IGBT in the existing converter layouts. The proposed AGD can alsominimize switching loss by controlling di/dt and dv/dt of device current and voltage respectively. The proposed active gate drive switching technique is termed as Quasi Zero Switching. Developedactive gate driver is tested in a double pulse test setup and in a 10 kVA two level voltage source inverter driving an induction motorload.
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