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Design of High Speed Continuous Time Delta Sigma Modulators using a Time Interleaved Quantizer “

December 11, 2015 @ 3:00 pm - 4:00 pm

Speaker :   Ankesh Jain (EE09D011 )

Abstract :

Continuous-time Delta Sigma Modulators based on 1-bit quantizers with FIR feedback combine the advantages of single-bit and multibit operation. At GHz clock rates, even the FIR-DAC approach begins to run into difficulties due to the limited time available for regeneration. This work uses a time-interleaved 1-bit ADC and 8-tap FIR-DACs to address this problem. Digital calibration (implemented off-chip) addresses mismatch in the interleaved sections, and rise-fall asymmetry in the feedback DAC waveforms.

Experimental results from fabricated chips demonstrate an ADC that
achieves true 11 bit performance in 60MHz bandwidth when clocked at  6 GHz in a UMC-65nm low leakage process, while consuming about 13mW.

Details

Date:
December 11, 2015
Time:
3:00 pm - 4:00 pm
Event Category:

Venue

ESB 244

Organizer

Prof. Shanthi Pavan
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