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Characterization of High Speed Continuous time Delta Sigma modulators using Duobinary coding

December 10, 2015 @ 3:00 pm - 4:30 pm

Speaker :   Ankesh Jain (EE09D011)


Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and  reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feed-through effects.  Experimental results from a test chip in 90nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing  single-bit CTDSM from 3.6 GHz to 4.4 GHz.


December 10, 2015
3:00 pm - 4:30 pm
Event Category:


ESB 244


Prof. Shanthi Pavan
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