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A two-channel ADC using a Delta-Sigma modulator without reset and a modulated-sinc-sum filter

September 16, 2019 @ 11:00 am - 12:00 pm

Date: 16th September 2019.

Time: 11:00am.

Venue: ESB244, Department of Electrical Engineering.

Speaker: R.S. Ashwin Kumar (EE13D058).

Guide: Dr. Nagendra Krishnapura.




Delta-Sigma ADCs are popular due to their ability to achieve high resolutions. But the intrinsic memory present in the ADC prevents it from being deployed in multiplexed (multi-channel) environments. The conventional way around this problem is to reset the memory elements in the ADC before the start of every conversion cycle. However, this intermittent operation compromises on the achievable signal-to-quantization noise ratio (SQNR) and the signal-to-noise ratio (SNR).


In this work, we propose a new method that lets a Delta-Sigma ADC to be used in a multiplexed environment without resetting its states or without requiring any additional analog design changes. We show that using the proposed “modulated-sinc-sum digital filter” at the output, a Delta-Sigma ADC can perform multi-channel A/D conversion. To demonstrate this, a two-channel ADC based on the proposed technique is designed and fabricated in a 180nm CMOS process. Clocked at 6.144MHz, with a channel-bandwidth of 22kHz, the designed ADC consumes 1.53mW/channel from a 1.8V supply. The measured SNR and Dynamic range (DR) are 94.4dB and 98.5dB, respectively. The measured inter-channel cross-talk is less than -94dBc across the entire bandwidth


September 16, 2019
11:00 am - 12:00 pm
Event Category:


ESB – 244
Electrical Engineering, IITM
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