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A power efficient CMOS receiver for OOK wireless link

July 10, 2015 @ 4:00 pm - 5:00 pm

Speaker: Anoop Narayan Bhat


                     Need for low cost, power efficient, robust and high speed short distance wireless communication implementation is increasing since electronic devices are becoming wireless enabled. A communication technique is proposed to achieve high data rate in receivers with low bandwidth circuits. The technique is implemented in chip to chip wireless communication and an RF receiver with 130 MHz front end circuit bandwidth is designed to achieve 400 Mbps data rate using 2 GHz carrier. Architecture of the receiver is presented and specification of individual blocks are derived.

                         Receiver consists of the peak detector to downconvert the RF signal. Generally either positive or negative peak detector is used for this high speed operation. Because of this, only half of the peak to peak input sinusoidal signal amplitude is used for peak detection. In this work, a technique is proposed to utilize full swing of the input sinusoid using both the types of peak detectors. This improves the gain in the receiver signal chain by 6 dB.
Receiver circuit is implemented in 180 nm CMOS process and fabricated. Receiver occupies an area of 0.8 mm×0.6 mm in the chip. Receiver is tested and data rate of 500 Mbps is achieved with 5.7 mW power consumption(11.4 pJ/bit).


July 10, 2015
4:00 pm - 5:00 pm
Event Category:


ESB 244


Dr. Nagendra Krishnapura
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